tag:blogger.com,1999:blog-87558903382878259492024-03-19T14:50:55.481-07:00WEH..buatlah kejeWindahttp://www.blogger.com/profile/11890708414448602573noreply@blogger.comBlogger3125tag:blogger.com,1999:blog-8755890338287825949.post-46730898414051418592010-02-16T19:51:00.000-08:002010-02-16T22:49:08.382-08:00inverterinverter <div><div>1.Selepas anda melukis bentangan inverter, Save layout dan cell. Buat design rules check (drc)</div><div>dan pastikan design anda 0 errors. Fail .drc ini anda perlu sertakan dalam report anda.<img id="BLOGGER_PHOTO_ID_5439056654797922642" style="DISPLAY: block; MARGIN: 0px auto 10px; WIDTH: 317px; CURSOR: hand; HEIGHT: 400px; TEXT-ALIGN: center" alt="" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhqksyC26ZNsfsr4wqIY5FNIhuVNrsHiPe7wtxRw0aePV0hflXjVsY1o5XoGuyhtH9Y15WBVtR-vW2GFotfxL3AKe3jVDr652Se0f-46H_4-KKfMUkO6Sno_lilg1YNSksxbehDaehfQVdq/s400/inveretr.JPG" border="0" /></div><br /><br /><div>2. Lakukan <em>cross-section. </em>Pastikan include sekali morbn20 dan buat perbincangan mengenai cross section dalam report anda.<br /></div><img id="BLOGGER_PHOTO_ID_5439057306570355970" style="DISPLAY: block; MARGIN: 0px auto 10px; WIDTH: 400px; CURSOR: hand; HEIGHT: 286px; TEXT-ALIGN: center" alt="" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiF1Z2vU1pNJ-TioxCqFX6F48n-fL8XcZE9zxah7XYw7V9ENij-ptxBepHZYlILjP1Tih4gIMfeocAU4U80awp3TKB0bcuT3GZW0055dsxgfnDtKlfED-TEXGuA2PME54pgmm3NdwueapoI/s400/inveretr7.JPG" border="0" /><br /><br /><p>3. Lakukan <em>extract. </em>Ikut arahan pensyarah didalam kelas.<br />4. Buka fail .spc .Pastikan node names wujud. Copy semua aturcara dan paste dalam notepad. Save as<strong> <em>inverter.cir . </em></strong><br />5. Lihat aturcara dibawah. Bandingkan spc anda dgn aturcara dibawah...Ada yg perlu diubah. Tulisan biru perlu didelete..Manakala tulisan merah adalah tambahan pada aturcara..</p><br /><p></p><br /><p>------------------------------------------------------------------------------------------------<br />* Circuit Extracted by Tanner Research's L-Edit V7.12 / Extract V4.00 ;<br />* TDB File: C:\Documents and Settings\Winda\Desktop\LAB_E5163\INVERTER, Cell: INVERTER<br />* Extract Definition File: C:\Documents and Settings\Winda\My Documents\L-Edit Student v7.12\mosis\morbn20.ext<br />* Extract Date and Time: 01/13/2010 - 10:55<br /><span style="color:#3366ff;">.include morbn20.md<br /></span><br /><span style="color:#3366ff;">* WARNING: Layers with Unassigned AREA Capacitance.<br />* <n><br />* <npn><br />* <allsubs><br />* <poly><br />* <poly><br />* <poly2><br />* <poly2><br />* <n><br />*<br /><p><br />* <n><br />*<br /><p><br />*<br /><p><br />* <subs><br />* <lpnp><br />* <pnp><br />* <vpnp><br />*<br /><p><br />* WARNING: Layers with Unassigned FRINGE Capacitance.<br />* <n><br />* <npn><br />* <ndiff><br />* <allsubs><br />* <poly><br />* <poly><br />* <poly2><br />* <poly2><br />* <n><br />*<br /><p><br />* <pdiff><br />* <n><br />*<br /><p><br />*<br /><p><br />* <poly1-poly2><br />* <subs><br />* <pad><br />* <metal1><br />* <lpnp><br />* <pnp><br />* <vpnp><br />* <metal2><br />*<br /><p><br />* WARNING: Layers with Zero Resistance.<br />* <n><br />* <npn><br />* <allsubs><br />* <poly><br />* <poly2><br />*<br /><p><br />* <poly1-poly2><br />* <nmos><br />* <pmos><br />* <subs><br />* <pad><br />* <lpnp><br />* <pnp><br />* <vpnp><br />*<br /><p><br /><br /></span>* NODE NAME ALIASES<br />* 1 = VDD (20,47)<br />* 2 = VSS (23,-16)<br />* 3 = OUTPUT (34.5,13)<br />* 4 = INPUT (7.5,13)</p><p><br />M5 OUTPUT INPUT VDD VDD PMOS L=2u W=11u AD=66p PD=34u AS=55p PS=32u </p><p>* M5 DRAIN GATE SOURCE BULK (23 26 34 28) </p><p>M6 VSS INPUT OUTPUT VSS NMOS L=2u W=10u AD=70p PD=34u AS=60p PS=32u </p><p>* M6 DRAIN GATE SOURCE BULK (23 0 33 2) </p><p><span style="color:#3366ff;">* Pins of element D7 are shorted: </span></p><p><span style="color:#3366ff;">* D7 VSS VSS D_lateral AREA=10p </span></p><p><span style="color:#3366ff;">* D7 PLUS MINUS (23 -7 33 -6) </span></p><p><span style="color:#3366ff;">* Pins of element D8 are shorted:</span></p><p><span style="color:#3366ff;"> * D8 VDD VDD D_lateral AREA=11p </span></p><p><span style="color:#3366ff;">* D8 PLUS MINUS (23 33 34 34) </span></p><p><span style="color:#ff0000;">*MENYATAKAN GELOMBANG MASUKAN<br />VVDD VDD 0 5<br />VVSS VSS 0 0</span><br /><br /><span style="color:#ff0000;">*MENYATAKAN GELOMBANG VOLTAN MASUKAN<br />VIN INPUT VSS pulse (5 0 0 1n 1n 0.5u 1u)<br /><br />*SURUH PSPICE BUAT ANALISIS TRANSIENT SETIAP 2ns DARI 0 HINGGA 8us<br />.tran 2n 8u<br />.probe<br /><br />* THESE ARE TYPICAL SCNA SPICE LEVEL 2 PARAMETERS<br />.MODEL NMOS NMOS LEVEL=2 LD=0.250000U TOX=417.000008E-10<br />+ NSUB=6.108619E+14 VTO=0.825008 KP=4.919000E-05 GAMMA=0.172<br />+ PHI=0.6 UO=594 UEXP=6.682275E-02 UCRIT=5000<br />+ DELTA=5.08308 VMAX=65547.3 XJ=0.250000U LAMBDA=6.636197E-03<br />+ NFS=1.98E+11 NEFF=1 NSS=1.000000E+10 TPG=1.000000<br />+ RSH=32.740000 CGDO=3.105345E-10 CGSO=3.105345E-10 CGBO=3.848530E-10<br />+ CJ=9.494900E-05 MJ=0.847099 CJSW=4.410100E-10 MJSW=0.334060 PB=0.800000<br />* Weff = Wdrawn - Delta_W<br />* The suggested Delta_W is -0.25 um<br />.MODEL PMOS PMOS LEVEL=2 LD=0.227236U TOX=417.000008E-10<br />+ NSUB=1.056124E+16 VTO=-0.937048 KP=1.731000E-05 GAMMA=0.715<br />+ PHI=0.6 UO=209 UEXP=0.233831 UCRIT=47509.9<br />+ DELTA=1.07179 VMAX=100000 XJ=0.250000U LAMBDA=4.391428E-02<br />+ NFS=3.27E+11 NEFF=1.001 NSS=1.000000E+10 TPG=-1.000000<br />+ RSH=72.960000 CGDO=2.822585E-10 CGSO=2.822585E-10 CGBO=5.292375E-10<br />+ CJ=3.224200E-04 MJ=0.584956 CJSW=2.979100E-10 MJSW=0.310807 PB=0.800000<br />* Weff = Wdrawn - Delta_W<br />* The suggested Delta_W is -1.14 um_</span></p><p>Cpar1 VDD 0 <span style="color:#3366ff;">C=</span>30.708f<br />Cpar2 VSS 0 <span style="color:#3366ff;">C=</span>28.035f<br />Cpar3 OUTPUT 0 <span style="color:#3366ff;">C=</span>31.582f<br />Cpar4 INPUT 0 <span style="color:#3366ff;">C=</span>9E-016 </p><p><span style="color:#ff0000;"><br /></span>* Total Nodes: 4<br />* Total Elements: 8<br />* Extract Elapsed Time: 0 seconds<br />.END</p><br />------------------------------------------------------------------------------------------------<br /><p></p><br /><br /><p>6. Tulisan yang merah tu kalau taip balik mungkin juling mata kamu, makanya copy paste sahaja....Jgn lupa save balik.....cir</p><br /><br /><p>7. Buka software ORCAD dan open fail inverter.cir . Klik RUN..harap2 takde error...kalau ada cari lah sendiri...jika tiada error, akan keluar paparan output automatik. Pelajar perlu masukkan data dan ini akan ditunjukkan oleh pensyarah didalam kelas....<img id="BLOGGER_PHOTO_ID_5439061174308483442" style="DISPLAY: block; MARGIN: 0px auto 10px; WIDTH: 400px; CURSOR: hand; HEIGHT: 288px; TEXT-ALIGN: center" alt="" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiV5RvEx85WeyqmgJclrLWyV44s80K4RaYzb1t0NHYGnjFl01UEQBeYNjXQNzft78sHQU4awFUMvGAPQs2DhCnmm4Qhe7ojF6VMZiWBYC7db-ZY_wenCjpulXOm1rqpeKLgAdP3CDG3xzcA/s400/inveretrresukt.JPG" border="0" /></p></div>Windahttp://www.blogger.com/profile/11890708414448602573noreply@blogger.com0tag:blogger.com,1999:blog-8755890338287825949.post-11825922404669103502009-10-19T19:39:00.000-07:002009-10-19T19:55:13.516-07:00NAND 4 input<strong>LAB NAND 4 input</strong><br /><strong><br /></strong><br /><strong></strong><br /><br /><br />*Dalam perbincangan sila sertakan jadual kebenaran, static CMOS logic, euler path dan stick diagram.<br /><br /><br /><br /><br /><br />Lukis bentangan CMOS NAND 4 input seperti yang disertakan didalam labsheet.<br /><br /><br /><br /><p><img id="BLOGGER_PHOTO_ID_5394507441770075778" style="DISPLAY: block; MARGIN: 0px auto 10px; WIDTH: 400px; CURSOR: hand; HEIGHT: 374px; TEXT-ALIGN: center" alt="" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgyBMArS8F9SbWCfcISDJI8AGhfk40w9lRzCrQgHf9D4OG-W07VsJ4oCQkM9EJdA7Oc0j0EPQn35ZpWJGm6qIDUqqjKp_hfanbgx96ndQgJ4_1g1ppAyZp1aoKZOLSOR4MbbmTRwzwu11OM/s400/1.JPG" border="0" />1. Rename cell as NAND_4. Click Cell - Rename - NAND_4</p><p>2.Save as NAND_4.</p><p>3. Make sure all the ports are in the correct layer. Click Edit - Edit Object(s) - choose layer (<strong>vdd=vss=output=inputs=metal1)</strong></p><p>4. Make sure the layout are free from error by doing drc. Click tools - drc...</p><p>5. Do cross section. Click tools - cross section. Before that you must have <em>morbn20 </em>file. Get from your lecturer.</p><p>6. Do extract. Click tools - extract. Extract also need morbn20 file and spc file will be extract. Spc file are needed to simulate your layout using P-spice. </p><p><br /> </p>Windahttp://www.blogger.com/profile/11890708414448602573noreply@blogger.com0tag:blogger.com,1999:blog-8755890338287825949.post-73216298612479889662009-10-13T18:41:00.000-07:002009-10-19T20:23:54.276-07:00simulation NAND_4<div align="center"><strong>IC Simulation (example:nand 4 input)</strong></div><div align="left"><br />Steps :<br />1. Select the nand_4 layout<br />2. Click Tools > Extract runs a general device extractor.<br />3. At General tab, choose extract definition file from extract folder and select morbin20.ext and </div><div align="left">save it in your folder (figure 1)<br />4. Extract also the parasitic capacitance. When pop up window appear, click at the Output tab </div><div align="left">and choose “Write nodal parasitic capacitance”. Give an instruction only capacitance which </div><div align="left">less than 0.5 femtofarad can be ignored. Fill in the value of 0.5 into the box “Ignore nodal </div><div align="left">parasitic capacitance less than”. (see figure 2 below and follow the instruction as the figure </div><div align="left">showed)<br />5. Do not label all devices. Box “Label all devices” must empty.<br />6. After that click Run. If has a warning appear after done this instruction, then click “Ignore </div><div align="left">all”. (figure 3)<br />7. Open the file NAND-4.spc by select the file of type as Spice file (.spc). Then click at the </div><div align="left">NAND_4 file >open.(figure 4)<br />8. Copy the NAND_4.spc and paste it in notepad. Then save the notepad as NAND_4.cir<br />9. Modified the file listing produce from NAND_4.spc to NAND_4.cir. (see listing file .spc and .cir </div><div align="left">and compare it, you will know which part of the file must be added or discard)<br />10. Simulate the circuit using PSpice software.<br />11. Open PSpice_AD<br />12. Click file open/NAND-4.cir . Pspice AD window will appear and notes Reading and checking </div><div align="left">circuit is shown.<br />13. If the checking completed successfully, select File>Run Probe, at this time the black </div><div align="left">graph will appear. If the checking unsuccessfully, select File>examine output, at this time </div><div align="left">any errors and listing value generated from the extraction file inverter.cir are shown with </div><div align="left">dollar sign.<br />14. Plot the graph by selecting the add plot menu 4 times. (figure 5)<br />15. Then select Trace >add then thick for Analog and Voltage.<br />16. Trace the waveform variable for Input, Output, VDD and Vss. (figure 6)<br />17. Your output waveform must tally with truth table.<br /></div><div align="center"><br /></div><img id="BLOGGER_PHOTO_ID_5392266560086637282" style="DISPLAY: block; MARGIN: 0px auto 10px; WIDTH: 400px; CURSOR: hand; HEIGHT: 251px; TEXT-ALIGN: center" alt="" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhnrpqe7gxnb0LzGq9mrj72EYm-vcZeGChDS5H9y4hkY5unjFXE3oIAYGKN3jyXZdd9dSKemQtrnuApeg7K6OsTbEUBJuAOvigMH0ARi-H6VXcwfi7h38rqBOAqFSHzVNem2Q9d5r53xSQd/s400/figure1.JPG" border="0" /> <div align="left">Figure 1<br /><br />Output tab<br />*Select all the comments<br />*Write nodes as Names<br />* Write nodal parasitic capacitance”. Give an instruction only capacitance which less than 0.5 femtofarad can be ignored. Fill in the value of 0.5 into the box </div><div align="left"></div><p><img id="BLOGGER_PHOTO_ID_5392271250871122610" style="DISPLAY: block; MARGIN: 0px auto 10px; WIDTH: 294px; CURSOR: hand; HEIGHT: 287px; TEXT-ALIGN: center" alt="" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgckpXX30WmdYBKuBn3dGGpIWMFHrgc6eRKj3_6rqh1aPaYqCUUta-0vPIYFbnOo_SVFB57cH_8-1Yah1KfaVydeLyQhumVbsgVOhLN1qlcnTwpq4OUbmqWkiOw8tL8Nz-sg4jhaFWPDOHA/s400/figure2.JPG" border="0" /><br />Figure 2 </p><p><img id="BLOGGER_PHOTO_ID_5392272667917361682" style="DISPLAY: block; MARGIN: 0px auto 10px; WIDTH: 385px; CURSOR: hand; HEIGHT: 245px; TEXT-ALIGN: center" alt="" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhuibusony2hbLfirccIo9QQXXtCT22InH2jsbMnUYI0wedS2RpdBusxemLhX2E0GqQEY293lr5oTmI6C0wR14p1ZCT8amG6zTJfS3jdEWkm7tNwWY6JLmfTOlNjBagBZJlB5pGz0i3JK-n/s400/figure3.JPG" border="0" /><br />Figure 3 </p><p><img id="BLOGGER_PHOTO_ID_5392272675068603346" style="DISPLAY: block; MARGIN: 0px auto 10px; WIDTH: 290px; CURSOR: hand; HEIGHT: 219px; TEXT-ALIGN: center" alt="" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjZTwUTmTPMn4HNOxWy1FVxcKZv7nQWQkFKjC9wfAeCa4mAEPRKiRwh_Ou_3sYbkYYWKm_O_iv2pLt5PqZKU-TJpZK31vYgtOUwJqe1vfYs7PiuXX9ftkWOpfrxe6x8Lwrf5dahJwHIvmAC/s400/figure4.JPG" border="0" /><br />Figure 4 </p><p> </p><p><span style="color:#000099;"></span><br /><br /><strong>NAND_4.spc in Ledit <span style="color:#3333ff;">(perhatikan bold biru adalah yg perlu dibuang semasa edit)<br /></span></strong>* Circuit Extracted by Tanner Research's L-Edit V7.12 / Extract V4.00 ;* TDB File: C:\Documents and Settings\Winda\My Documents\labledit\NAND4, Cell: NAND4* Extract Definition File: D:\untuk copy dlm pendrive\My Document\E5163\mus\L-Edit Student v7.12\mosis\morbn20.ext* Extract Date and Time: 02/18/2009 - 17:11</p><p><br /><strong><span style="color:#3333ff;">.include morbn20.md</span></strong></p><p align="justify"><br /><strong><span style="color:#3333ff;">* WARNING: Layers with Unassigned AREA Capacitance.</span></strong></p><p align="justify"><strong><span style="color:#3333ff;">* <allsubs></span></strong></p><p><strong><span style="color:#3333ff;">* <lpnp></span></strong></p><p><strong><span style="color:#3333ff;">* <n></span></strong></p><p><strong><span style="color:#3333ff;">* <pnp></span></strong></p><p><strong><span style="color:#3333ff;">* <vpnp></span></strong></p><p><strong><span style="color:#3333ff;">* <npn></span></strong></p><p><strong><span style="color:#3333ff;">* <poly></span></strong></p><p><strong><span style="color:#3333ff;">* <poly></span></strong></p><p><strong><span style="color:#3333ff;">* <poly2></span></strong></p><p><strong><span style="color:#3333ff;">* <poly2></span></strong></p><p><strong><span style="color:#3333ff;">* <n></span></strong></p><p><strong><span style="color:#3333ff;">* <p></span></strong></p><p><strong><span style="color:#3333ff;">* <n></span></strong></p><p><strong><span style="color:#3333ff;">* <p></span></strong></p><p><strong><span style="color:#3333ff;">* <p></span></strong></p><p><strong><span style="color:#3333ff;">* <subs></span></strong></p><p><strong><span style="color:#3333ff;">* <p><br /></span></strong></p><p>* NODE NAME ALIASES</p><p>* 1 = A (16,782.5)</p><p>* 2 = B (26.5,782.5)</p><p>* 3 = C (36.5,782.5)</p><p>* 4 = D (46.5,782.5)</p><p>* 5 = VDD (2.5,852.5)</p><p>* 6 = OUTPUT (2,813.5)</p><p>* 7 = VSS (10.5,772)</p><p><br />Cpar1 A 0 <strong><span style="color:#3333ff;">C=</span></strong>8E-016</p><p>Cpar2 B 0 <strong><span style="color:#3333ff;">C=</span></strong>7E-016</p><p>Cpar3 C 0 <strong><span style="color:#3333ff;">C=</span></strong>7E-016</p><p>Cpar4 D 0 <strong><span style="color:#3333ff;">C=</span></strong>7E-016</p><p>Cpar5 VDD 0 <span style="color:#3333ff;"><strong>C=</strong></span>167.735f</p><p>Cpar6 OUTPUT 0 <strong><span style="color:#3333ff;">C=</span></strong>113.0845f</p><p>Cpar7 VSS 0 <span style="color:#3333ff;"><strong>C=</strong></span>61.864f</p><p>Cpar8 8 0 <strong><span style="color:#3333ff;">C=</span></strong>12.288f</p><p>Cpar9 9 0 <strong><span style="color:#3333ff;">C=</span></strong>12.288f</p><p>Cpar10 10 0 <strong><span style="color:#3333ff;">C=</span></strong>12.288f</p><p><br />M11 VDD D OUTPUT VDD PMOS L=2u W=17u AD=408p PD=150u AS=272p PS=100u </p><p>* M11 DRAIN GATE SOURCE BULK (53 825 55 842) </p><p>M12 OUTPUT C VDD VDD PMOS L=2u W=17u AD=272p PD=100u AS=408p PS=150u </p><p>* M12 DRAIN GATE SOURCE BULK (43 825 45 842) </p><p>M13 VDD B OUTPUT VDD PMOS L=2u W=17u AD=408p PD=150u AS=272p PS=100u</p><p> * M13 DRAIN GATE SOURCE BULK (33 825 35 842) </p><p>M14 OUTPUT A VDD VDD PMOS L=2u W=17u AD=272p PD=100u AS=408p PS=150u </p><p>* M14 DRAIN GATE SOURCE BULK (23 825 25 842) </p><p>M15 OUTPUT D 10 VSS NMOS L=2u W=12u AD=96p PD=40u AS=96p PS=40u </p><p>* M15 DRAIN GATE SOURCE BULK (53 793 55 805) </p><p>M16 10 C 9 VSS NMOS L=2u W=12u AD=96p PD=40u AS=96p PS=40u </p><p>* M16 DRAIN GATE SOURCE BULK (43 793 45 805)</p><p> M17 9 B 8 VSS NMOS L=2u W=12u AD=96p PD=40u AS=96p PS=40u </p><p>* M17 DRAIN GATE SOURCE BULK (33 793 35 805) </p><p>M18 8 A VSS VSS NMOS L=2u W=12u AD=96p PD=40u AS=96p PS=40u </p><p>* M18 DRAIN GATE SOURCE BULK (23 793 25 805) </p><p><strong><span style="color:#3333ff;">* Pins of element D19 are shorted:</span></strong></p><p><strong><span style="color:#3333ff;">* D19 VSS VSS D_lateral AREA=12p</span></strong></p><p><strong><span style="color:#3333ff;">* D19 PLUS MINUS (15 793 16 805) </span></strong></p><p><span style="color:#3333ff;"><strong>* Pins of element D20 are shorted:</strong></span></p><p><span style="color:#3333ff;"><strong>* D20 VDD VDD D_lateral AREA=17p</strong></span></p><p><span style="color:#3333ff;"><strong>* D20 PLUS MINUS (14 825 15 842)</strong></span> </p><p><br />* Total Nodes: 10</p><p>* Total Elements: 20</p><p>* Extract Elapsed Time: 0 seconds.END<br /></p><p><br /><strong>NAND_4.cir modified from spice file Ledit</strong><br /><strong><span style="color:#ff0000;">tulisan merah (bold)</span></strong> adalah ditambah pada aturcara sila print kedua-dua aturcara ini dan bezakan apa yang ditambah dan yang dibuang. <strong><span style="color:#009900;">Perhatikan juga tulisan hijau, pastikan ciri2 adalah sama supaya simulation di P-spice tiada masalah</span></strong>.</p><p>* Circuit Extracted by Tanner Research's L-Edit V7.12 / Extract V4.00 ;* TDB File: C:\Documents and Settings\Winda\My Documents\labledit\NAND4, Cell: NAND4* Extract Definition File: D:\untuk copy dlm pendrive\My Document\E5163\mus\L-Edit Student v7.12\mosis\morbn20.ext* Extract Date and Time: 02/18/2009 - 17:11</p><p><br />* NODE NAME ALIASES</p><p>* <span style="color:#cc33cc;"> </span><span style="color:#6600cc;"> </span><span style="color:#009900;"><strong>1 = A</strong></span> (16,782.5)</p><p>* <span style="color:#009900;"><strong>2 = B</strong></span> (26.5,782.5)</p><p>* <strong><span style="color:#009900;">3 = C</span></strong> (36.5,782.5)</p><p>* <span style="color:#009900;"><strong> 4 = D</strong></span> (46.5,782.5)</p><p>* <strong><span style="color:#009900;"> 5 = VDD</span></strong> (2.5,852.5)</p><p>* <span style="color:#009900;"><strong>6 = OUTPUT</strong></span> (2,813.5)</p><p>* <strong><span style="color:#009900;">7 = VSS</span></strong> (10.5,772)</p><p><br />M11 VDD D OUTPUT VDD PMOS L=2u W=17u AD=408p PD=150u AS=272p PS=100u </p><p>* M11 DRAIN GATE SOURCE BULK (53 825 55 842) </p><p>M12 OUTPUT C VDD VDD PMOS L=2u W=17u AD=272p PD=100u AS=408p PS=150u </p><p>* M12 DRAIN GATE SOURCE BULK (43 825 45 842) </p><p>M13 VDD B OUTPUT VDD PMOS L=2u W=17u AD=408p PD=150u AS=272p PS=100u </p><p>* M13 DRAIN GATE SOURCE BULK (33 825 35 842) </p><p>M14 OUTPUT A VDD VDD PMOS L=2u W=17u AD=272p PD=100u AS=408p PS=150u </p><p>* M14 DRAIN GATE SOURCE BULK (23 825 25 842) </p><p>M15 OUTPUT D 10 VSS NMOS L=2u W=12u AD=96p PD=40u AS=96p PS=40u </p><p>* M15 DRAIN GATE SOURCE BULK (53 793 55 805) </p><p>M16 10 C 9 VSS NMOS L=2u W=12u AD=96p PD=40u AS=96p PS=40u </p><p>* M16 DRAIN GATE SOURCE BULK (43 793 45 805) </p><p>M17 9 B 8 VSS NMOS L=2u W=12u AD=96p PD=40u AS=96p PS=40u </p><p>* M17 DRAIN GATE SOURCE BULK (33 793 35 805) </p><p>M18 8 A VSS VSS NMOS L=2u W=12u AD=96p PD=40u AS=96p PS=40u </p><p>* M18 DRAIN GATE SOURCE BULK (23 793 25 805) </p><p><br /><span style="color:#ff0000;"><strong>***INPUT SIGNAL POWER AND GROUND</strong></span></p><p><span style="color:#ff0000;"><strong>VVDD VDD 0 5VVSS VSS 0 0</strong></span></p><p><br /><span style="color:#ff0000;"><strong>***INPUT SIGNAL VOLTAGE</strong></span></p><p><span style="color:#009900;"><strong>VIN1 A</strong></span> <strong><span style="color:#ff0000;">VSS 0 pulse (5 0 0 1n 1n 1.0u 2u]</span></strong></p><p><strong><span style="color:#009900;">VIN2 B</span></strong> <strong><span style="color:#ff0000;">VSS 0 pulse (5 0 0 1n 1n 0.5u 1u)</span></strong></p><p><strong><span style="color:#009900;">VIN3 C</span></strong> <strong><span style="color:#ff0000;">VSS 0 pulse (5 0 0 1n 1n 1.0u 2u)</span></strong></p><p><strong><span style="color:#009900;">VIN4 D</span></strong> <span style="color:#ff0000;"><strong>VSS 0 pulse (5 0 0 1n 1n 0.5u 1u)</strong></span></p><p><span style="color:#ff0000;"><strong>***************************volt 0 0 vpuncak2 1 2.tran 2n 8u.probe</strong></span></p><p><span style="color:#ff0000;"><strong>****************************masa penyelakuan dimana litar diselakukan setiap 2ns dan berakhir pada 8us</strong></span></p><p><br />Cpar1 A 0 8E-016</p><p>Cpar2 B 0 7E-016</p><p>Cpar3 C 0 7E-016</p><p>Cpar4 D 0 7E-016</p><p>Cpar5 VDD 0 167.735f</p><p>Cpar6 OUTPUT 0 113.0845f</p><p>Cpar7 VSS 0 61.864f</p><p>Cpar8 8 0 12.288f</p><p>Cpar9 9 0 12.288f</p><p>Cpar10 10 0 12.288f</p><p><br /><strong><span style="color:#ff0000;">* THESE ARE TYPICAL SCNA SPICE LEVEL 2 PARAMETERS.MODEL NMOS NMOS LEVEL=2 LD=0.250000U TOX=417.000008E-10+ NSUB=6.108619E+14 VTO=0.825008 KP=4.919000E-05 GAMMA=0.172+ PHI=0.6 UO=594 UEXP=6.682275E-02 UCRIT=5000+ DELTA=5.08308 VMAX=65547.3 XJ=0.250000U LAMBDA=6.636197E-03+ NFS=1.98E+11 NEFF=1 NSS=1.000000E+10 TPG=1.000000+ RSH=32.740000 CGDO=3.105345E-10 CGSO=3.105345E-10 CGBO=3.848530E-10+ CJ=9.494900E-05 MJ=0.847099 CJSW=4.410100E-10 MJSW=0.334060 PB=0.800000* Weff = Wdrawn - Delta_W* The suggested Delta_W is -0.25 um.MODEL PMOS PMOS LEVEL=2 LD=0.227236U TOX=417.000008E-10+ NSUB=1.056124E+16 VTO=-0.937048 KP=1.731000E-05 GAMMA=0.715+ PHI=0.6 UO=209 UEXP=0.233831 UCRIT=47509.9+ DELTA=1.07179 VMAX=100000 XJ=0.250000U LAMBDA=4.391428E-02+ NFS=3.27E+11 NEFF=1.001 NSS=1.000000E+10 TPG=-1.000000+ RSH=72.960000 CGDO=2.822585E-10 CGSO=2.822585E-10 CGBO=5.292375E-10+ CJ=3.224200E-04 MJ=0.584956 CJSW=2.979100E-10 MJSW=0.310807 PB=0.800000* Weff = Wdrawn - Delta_W* The suggested Delta_W is -1.14 um </span></strong></p><p><br />* Total Nodes: 10</p><p>* Total Elements: 20</p><p>* Extract Elapsed Time: 0 seconds.END<br /><br /></p><img id="BLOGGER_PHOTO_ID_5392272681317128722" style="DISPLAY: block; MARGIN: 0px auto 10px; WIDTH: 400px; CURSOR: hand; HEIGHT: 253px; TEXT-ALIGN: center" alt="" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh4rQWHqKJCeEG54VTCPr-NTNokQrW6UwNKpCMGCJN2fCkkWSmhiqOi7UOM1nRj-5zuBvoIVGqSeqx_y9RlwRNr996R7Xu0G9uRsLaJ4tyk1qxo0yIAZ6v9I6KUI88daMp2Ei54NfM6IdhV/s400/figure5.JPG" border="0" /> <p align="left"><br />Figure5<br /><br />* Select examine output will show us the detail any errors and listing value generated from the extraction file NAND_4.cir<br /></p><p><br /><strong>Result</strong><br />*Open Pspice A_D<br />*click file open/inverter.spc and the Pspice A_D window will appear and notes Reading and checking circuit is shown<br />*if the simulation processes are successful the Run probe and Examine output are ON.<br /><br />*Select run probe will show us the result of input and output waveform generated from the extraction file inverter.cir<br /></p><p align="center"><img id="BLOGGER_PHOTO_ID_5392272686905883426" style="DISPLAY: block; MARGIN: 0px auto 10px; WIDTH: 400px; CURSOR: hand; HEIGHT: 301px; TEXT-ALIGN: center" alt="" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEikwHfF4H1r-ntfOpJ37YXx4m-Yqrwi-w5HsXseQ6K7g2m4pNBVe4NnxhPmQrYMUfCdFNVhrIPGs2zBbndPaUgOFPpikmEAZbph7r-7HRMEJTrKvlz5bqeCiIU7ZFBTLUI8T6NWfkaOv8gS/s400/figure6.JPG" border="0" /> Figure 6 (ini adalah contoh waveform utk inverter)<br /></p>Windahttp://www.blogger.com/profile/11890708414448602573noreply@blogger.com0