*Dalam perbincangan sila sertakan jadual kebenaran, static CMOS logic, euler path dan stick diagram.
Lukis bentangan CMOS NAND 4 input seperti yang disertakan didalam labsheet.
1. Rename cell as NAND_4. Click Cell - Rename - NAND_4
2.Save as NAND_4.
3. Make sure all the ports are in the correct layer. Click Edit - Edit Object(s) - choose layer (vdd=vss=output=inputs=metal1)
4. Make sure the layout are free from error by doing drc. Click tools - drc...
5. Do cross section. Click tools - cross section. Before that you must have morbn20 file. Get from your lecturer.
6. Do extract. Click tools - extract. Extract also need morbn20 file and spc file will be extract. Spc file are needed to simulate your layout using P-spice.