IC Simulation (example:nand 4 input)
Steps :
1. Select the nand_4 layout
2. Click Tools > Extract runs a general device extractor.
3. At General tab, choose extract definition file from extract folder and select morbin20.ext and
save it in your folder (figure 1)
4. Extract also the parasitic capacitance. When pop up window appear, click at the Output tab
and choose “Write nodal parasitic capacitance”. Give an instruction only capacitance which
less than 0.5 femtofarad can be ignored. Fill in the value of 0.5 into the box “Ignore nodal
parasitic capacitance less than”. (see figure 2 below and follow the instruction as the figure
showed)
5. Do not label all devices. Box “Label all devices” must empty.
6. After that click Run. If has a warning appear after done this instruction, then click “Ignore
all”. (figure 3)
7. Open the file NAND-4.spc by select the file of type as Spice file (.spc). Then click at the
NAND_4 file >open.(figure 4)
8. Copy the NAND_4.spc and paste it in notepad. Then save the notepad as NAND_4.cir
9. Modified the file listing produce from NAND_4.spc to NAND_4.cir. (see listing file .spc and .cir
and compare it, you will know which part of the file must be added or discard)
10. Simulate the circuit using PSpice software.
11. Open PSpice_AD
12. Click file open/NAND-4.cir . Pspice AD window will appear and notes Reading and checking
circuit is shown.
13. If the checking completed successfully, select File>Run Probe, at this time the black
graph will appear. If the checking unsuccessfully, select File>examine output, at this time
any errors and listing value generated from the extraction file inverter.cir are shown with
dollar sign.
14. Plot the graph by selecting the add plot menu 4 times. (figure 5)
15. Then select Trace >add then thick for Analog and Voltage.
16. Trace the waveform variable for Input, Output, VDD and Vss. (figure 6)
17. Your output waveform must tally with truth table.
Figure 1
Output tab
*Select all the comments
*Write nodes as Names
* Write nodal parasitic capacitance”. Give an instruction only capacitance which less than 0.5 femtofarad can be ignored. Fill in the value of 0.5 into the box
Figure 2
Figure 3
Figure 4
NAND_4.spc in Ledit (perhatikan bold biru adalah yg perlu dibuang semasa edit)
* Circuit Extracted by Tanner Research's L-Edit V7.12 / Extract V4.00 ;* TDB File: C:\Documents and Settings\Winda\My Documents\labledit\NAND4, Cell: NAND4* Extract Definition File: D:\untuk copy dlm pendrive\My Document\E5163\mus\L-Edit Student v7.12\mosis\morbn20.ext* Extract Date and Time: 02/18/2009 - 17:11
.include morbn20.md
* WARNING: Layers with Unassigned AREA Capacitance.
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* NODE NAME ALIASES
* 1 = A (16,782.5)
* 2 = B (26.5,782.5)
* 3 = C (36.5,782.5)
* 4 = D (46.5,782.5)
* 5 = VDD (2.5,852.5)
* 6 = OUTPUT (2,813.5)
* 7 = VSS (10.5,772)
Cpar1 A 0 C=8E-016
Cpar2 B 0 C=7E-016
Cpar3 C 0 C=7E-016
Cpar4 D 0 C=7E-016
Cpar5 VDD 0 C=167.735f
Cpar6 OUTPUT 0 C=113.0845f
Cpar7 VSS 0 C=61.864f
Cpar8 8 0 C=12.288f
Cpar9 9 0 C=12.288f
Cpar10 10 0 C=12.288f
M11 VDD D OUTPUT VDD PMOS L=2u W=17u AD=408p PD=150u AS=272p PS=100u
* M11 DRAIN GATE SOURCE BULK (53 825 55 842)
M12 OUTPUT C VDD VDD PMOS L=2u W=17u AD=272p PD=100u AS=408p PS=150u
* M12 DRAIN GATE SOURCE BULK (43 825 45 842)
M13 VDD B OUTPUT VDD PMOS L=2u W=17u AD=408p PD=150u AS=272p PS=100u
* M13 DRAIN GATE SOURCE BULK (33 825 35 842)
M14 OUTPUT A VDD VDD PMOS L=2u W=17u AD=272p PD=100u AS=408p PS=150u
* M14 DRAIN GATE SOURCE BULK (23 825 25 842)
M15 OUTPUT D 10 VSS NMOS L=2u W=12u AD=96p PD=40u AS=96p PS=40u
* M15 DRAIN GATE SOURCE BULK (53 793 55 805)
M16 10 C 9 VSS NMOS L=2u W=12u AD=96p PD=40u AS=96p PS=40u
* M16 DRAIN GATE SOURCE BULK (43 793 45 805)
M17 9 B 8 VSS NMOS L=2u W=12u AD=96p PD=40u AS=96p PS=40u
* M17 DRAIN GATE SOURCE BULK (33 793 35 805)
M18 8 A VSS VSS NMOS L=2u W=12u AD=96p PD=40u AS=96p PS=40u
* M18 DRAIN GATE SOURCE BULK (23 793 25 805)
* Pins of element D19 are shorted:
* D19 VSS VSS D_lateral AREA=12p
* D19 PLUS MINUS (15 793 16 805)
* Pins of element D20 are shorted:
* D20 VDD VDD D_lateral AREA=17p
* D20 PLUS MINUS (14 825 15 842)
* Total Nodes: 10
* Total Elements: 20
* Extract Elapsed Time: 0 seconds.END
NAND_4.cir modified from spice file Ledit
tulisan merah (bold) adalah ditambah pada aturcara sila print kedua-dua aturcara ini dan bezakan apa yang ditambah dan yang dibuang. Perhatikan juga tulisan hijau, pastikan ciri2 adalah sama supaya simulation di P-spice tiada masalah.
* Circuit Extracted by Tanner Research's L-Edit V7.12 / Extract V4.00 ;* TDB File: C:\Documents and Settings\Winda\My Documents\labledit\NAND4, Cell: NAND4* Extract Definition File: D:\untuk copy dlm pendrive\My Document\E5163\mus\L-Edit Student v7.12\mosis\morbn20.ext* Extract Date and Time: 02/18/2009 - 17:11
* NODE NAME ALIASES
* 1 = A (16,782.5)
* 2 = B (26.5,782.5)
* 3 = C (36.5,782.5)
* 4 = D (46.5,782.5)
* 5 = VDD (2.5,852.5)
* 6 = OUTPUT (2,813.5)
* 7 = VSS (10.5,772)
M11 VDD D OUTPUT VDD PMOS L=2u W=17u AD=408p PD=150u AS=272p PS=100u
* M11 DRAIN GATE SOURCE BULK (53 825 55 842)
M12 OUTPUT C VDD VDD PMOS L=2u W=17u AD=272p PD=100u AS=408p PS=150u
* M12 DRAIN GATE SOURCE BULK (43 825 45 842)
M13 VDD B OUTPUT VDD PMOS L=2u W=17u AD=408p PD=150u AS=272p PS=100u
* M13 DRAIN GATE SOURCE BULK (33 825 35 842)
M14 OUTPUT A VDD VDD PMOS L=2u W=17u AD=272p PD=100u AS=408p PS=150u
* M14 DRAIN GATE SOURCE BULK (23 825 25 842)
M15 OUTPUT D 10 VSS NMOS L=2u W=12u AD=96p PD=40u AS=96p PS=40u
* M15 DRAIN GATE SOURCE BULK (53 793 55 805)
M16 10 C 9 VSS NMOS L=2u W=12u AD=96p PD=40u AS=96p PS=40u
* M16 DRAIN GATE SOURCE BULK (43 793 45 805)
M17 9 B 8 VSS NMOS L=2u W=12u AD=96p PD=40u AS=96p PS=40u
* M17 DRAIN GATE SOURCE BULK (33 793 35 805)
M18 8 A VSS VSS NMOS L=2u W=12u AD=96p PD=40u AS=96p PS=40u
* M18 DRAIN GATE SOURCE BULK (23 793 25 805)
***INPUT SIGNAL POWER AND GROUND
VVDD VDD 0 5VVSS VSS 0 0
***INPUT SIGNAL VOLTAGE
VIN1 A VSS 0 pulse (5 0 0 1n 1n 1.0u 2u]
VIN2 B VSS 0 pulse (5 0 0 1n 1n 0.5u 1u)
VIN3 C VSS 0 pulse (5 0 0 1n 1n 1.0u 2u)
VIN4 D VSS 0 pulse (5 0 0 1n 1n 0.5u 1u)
***************************volt 0 0 vpuncak2 1 2.tran 2n 8u.probe
****************************masa penyelakuan dimana litar diselakukan setiap 2ns dan berakhir pada 8us
Cpar1 A 0 8E-016
Cpar2 B 0 7E-016
Cpar3 C 0 7E-016
Cpar4 D 0 7E-016
Cpar5 VDD 0 167.735f
Cpar6 OUTPUT 0 113.0845f
Cpar7 VSS 0 61.864f
Cpar8 8 0 12.288f
Cpar9 9 0 12.288f
Cpar10 10 0 12.288f
* THESE ARE TYPICAL SCNA SPICE LEVEL 2 PARAMETERS.MODEL NMOS NMOS LEVEL=2 LD=0.250000U TOX=417.000008E-10+ NSUB=6.108619E+14 VTO=0.825008 KP=4.919000E-05 GAMMA=0.172+ PHI=0.6 UO=594 UEXP=6.682275E-02 UCRIT=5000+ DELTA=5.08308 VMAX=65547.3 XJ=0.250000U LAMBDA=6.636197E-03+ NFS=1.98E+11 NEFF=1 NSS=1.000000E+10 TPG=1.000000+ RSH=32.740000 CGDO=3.105345E-10 CGSO=3.105345E-10 CGBO=3.848530E-10+ CJ=9.494900E-05 MJ=0.847099 CJSW=4.410100E-10 MJSW=0.334060 PB=0.800000* Weff = Wdrawn - Delta_W* The suggested Delta_W is -0.25 um.MODEL PMOS PMOS LEVEL=2 LD=0.227236U TOX=417.000008E-10+ NSUB=1.056124E+16 VTO=-0.937048 KP=1.731000E-05 GAMMA=0.715+ PHI=0.6 UO=209 UEXP=0.233831 UCRIT=47509.9+ DELTA=1.07179 VMAX=100000 XJ=0.250000U LAMBDA=4.391428E-02+ NFS=3.27E+11 NEFF=1.001 NSS=1.000000E+10 TPG=-1.000000+ RSH=72.960000 CGDO=2.822585E-10 CGSO=2.822585E-10 CGBO=5.292375E-10+ CJ=3.224200E-04 MJ=0.584956 CJSW=2.979100E-10 MJSW=0.310807 PB=0.800000* Weff = Wdrawn - Delta_W* The suggested Delta_W is -1.14 um
* Total Nodes: 10
* Total Elements: 20
* Extract Elapsed Time: 0 seconds.END
Figure5
* Select examine output will show us the detail any errors and listing value generated from the extraction file NAND_4.cir
Result
*Open Pspice A_D
*click file open/inverter.spc and the Pspice A_D window will appear and notes Reading and checking circuit is shown
*if the simulation processes are successful the Run probe and Examine output are ON.
*Select run probe will show us the result of input and output waveform generated from the extraction file inverter.cir
Figure 6 (ini adalah contoh waveform utk inverter)
1. Rename cell as NAND_4. Click Cell - Rename - NAND_4
